1. Field of the Invention
The present invention relates to a gated clock generating circuit that outputs a clock signal while turning it on and off.
2. Description of the Prior Art
In a semiconductor integrated circuit that operates in synchronism with a clock signal (hereinafter such a circuit will be referred to as a “clock-synchronous circuit”), too large a difference between the delay times with which the clock signal is fed to different flip-flops (hereinafter such a difference will be referred to as a “skew”) causes a fault such as nonfunctioning or malfunctioning of the circuit. To avoid this, clock-synchronous circuits are generally given a synchronized design.
A synchronized design consists in feeding an external clock signal directly to the clock input terminals of flip-flops within a circuit without dividing, turning on or off, or inverting the clock signal inside the circuit, and in addition arranging circuit elements and interconnecting them (hereinafter referred to as “arrangement and interconnection”) so as to minimize skews in the clock signal.
However, in a clock-synchronous circuit so designed, the clock signal is fed to all the flip-flops simultaneously all the time. This increases the electric power consumption of the flip-flops, and thus increases the electric power consumption of the clock-synchronous circuit as a whole.
One effective way proposed to reduce the electric power consumption of a clock-synchronous circuit is to provide it with a gated clock generating circuit so that a gated clock signal generated by the gated clock generating circuit is fed to the clock input terminals of flip-flops that need not operate under certain conditions.
FIGS. 14 and 16 show examples of the configuration of conventional gated clock generating circuits.
First, the gated clock generating circuit shown in FIG. 14 will be described. A clock signal CLK1 is received at an input terminal 1, which is connected through a buffer gate BUF1 to the input terminal of a buffer gate BUF2 and to the input terminal of a buffer gate BUF3.
The output terminal of the buffer gate BUF2 is connected to the clock input terminal of a flip-flop FF1. The output terminal of the buffer gate BUF3 is connected to the second input terminal of an AND gate AN1.
A data signal Data1 is received at an input terminal 2, which is connected to the data input terminal of the flip-flop FF1. The output terminal of the flip-flop FF1 is connected to the first input terminal of the AND gate AN1. The output terminal of the AND gate AN1 is connected to an output terminal 3, at which a gated clock signal GCLK1 is fed out.
Now, the operation of the gated clock generating circuit configured in this way will be described with reference to the circuit configuration diagram of FIG. 14 and a timing chart of FIG. 15A. The clock signal CLK1 received at the input terminal 1, through the buffer gate BUF1 and the buffer gate BUF2, reaches the clock input terminal of the flip-flop FF1. The data signal Data1 received at the input terminal 2 reaches the data input terminal of the flip-flop FF1. As a result, from the output terminal 1 of the flip-flop FF1 to the first input terminal of the AND gate AN1 is fed a gate signal Gate1, which has, as shown in FIG. 15A, a waveform having inversion points of the data signal Data1 delayed up to rising edges of the clock signal CLK1.
The clock signal CLK1 received at the input terminal 1 reaches the second input terminal of the AND gate AN1 as well. Thus, the AND gate AN1 outputs to the output terminal 3 the gated clock signal GCLK1, which is the AND of the gate signal Gate1 and the clock signal CLK1.
In this way, by designating with the input of the data signal the period in which the clock signal is needed, it is possible to output the clock signal only in the period in which it is needed, in the form of the gated clock signal GCLK1.
Next, the gated clock generating circuit shown in FIG. 16 will be described. A clock signal CLK2 is received at an input terminal 4, which is connected to the input terminal of an inverter INV2 and to the input terminal of a buffer gate BUF5.
The output terminal of the inverter INV2 is connected through a buffer gate BUF4 to the clock input terminal of a flip-flop FF3. The output terminal of the buffer gate BUF5 is connected to the second input terminal of an AND gate AN3.
A data signal Data2 is received at an input terminal 5, which is connected to the data input terminal of the flip-flop FF3. The output terminal of the flip-flop FF3 is connected to the first input terminal of the AND gate AN3. The output terminal of the AND gate AN3 is connected to an output terminal 6, at which a gated clock signal GCLK2 is fed out.
Now, the operation of the gated clock generating circuit configured in this way will be described with reference to the circuit configuration diagram of FIG. 16 and a timing chart of FIG. 17A. The clock signal CLK2 received at the input terminal 4 is inverted by the inverter INV2, and then, through the buffer gate BUF4, reaches the clock input terminal of the flip-flop FF3. The data signal Data2 received at the input terminal 5 reaches the data input terminal of the flip-flop FF3. As a result, from the output terminal of the flip-flop FF3 to the first input terminal of the AND gate AN3 is fed a gate signal Gate3, which has, as shown in FIG. 17A, a waveform having inversion points of the data signal Data2 delayed up to trailing edges of the clock signal CLK2.
The clock signal CLK2 received at the input terminal 4, through the buffer gate BUF5, reaches the second input terminal of the AND gate AN3 as well. Thus, the AND gate AN3 outputs to the output terminal 6 the gated clock signal GCLKC2, which is the AND of the gate signal Gate3 and the clock signal CLK2.
In this way, by designating with the input of the data signal the period in which the clock signal is needed, it is possible to output the clock signal only in the period in which it is needed, in the form of the gated clock signal GCLK2.
However, different delays are produced depending on arrangement and interconnection, and therefore an edge of the gate signal reaching the first input terminal of the AND gate outputting the gated clock signal does not necessarily coincides with the corresponding edge of the clock signal reaching the second input terminal of the same AND gate as shown in FIG. 15A or 17A.
For example, in the gated clock generating circuit shown in FIG. 14, if the clock signal CLK1 reaches the AND gate AN1 earlier than the gate signal Gate1 does, then, as shown in FIG. 15B, in the vicinity of an inversion points of the gate signal Gate1, there is created a period t1 in which the clock signal CLK1 and the gate signal Gate1 are simultaneously high. This produces a glitch in the gated clock signal GCLK1 in the period t1. By contrast, if the gate signal Gate1 reaches the AND gate AN1 earlier than the clock signal CLK1 does, then, as shown in FIG. 15C, in the vicinity of an inversion points of the gate signal Gate1, no period is created in which the clock signal CLK1 and the gate signal Gate1 are simultaneously high. Thus, no glitch is produced in the gated clock signal GCLK1.
On the other hand, in the gated clock generating circuit shown in FIG. 16, if the gate signal Gate3 reaches the AND gate AN3 earlier than the clock signal CLK2 does, then, as shown in FIG. 17C, in the vicinity of an inversion points of the gate signal Gate3, there is created a period t2 in which the clock signal CLK2 and the gate signal Gate3 are simultaneously high. This produces a glitch in the gated clock signal GCLK2 in the period t2. By contrast, if the clock signal CLK2 reaches the AND gate AN3 earlier than the gate signal Gate3 does, then, as shown in FIG. 17B, in the vicinity of an inversion points of the gate signal Gate3, no period is created in which the clock signal CLK2 and the gate signal Gate3 are simultaneously high. Thus, no glitch is produced in the gated clock signal GCLK2.
Such glitches in the gated clock signal may cause malfunctioning of the circuit to which it is fed. To avoid this, in a clock-synchronous circuit, after arrangement and interconnection, it is essential to check the delay times produced in the clock and gate signals before they reach the AND gate outputting the gated clock signal. If glitches are found to appear in the gated clock signal, it is inevitable to retry arrangement and interconnection, as by inserting redundant circuits, or even to redesign the whole circuit in order to adjust the delay times in the clock and gate signals.